1. Field of the Invention
This invention relates to computing systems, and more particularly, to efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC).
2. Description of the Relevant Art
A system-on-a-chip (SOC) integrates multiple functions into a single integrated chip substrate to meet increasing processing demands of embedded system applications. The functions may include digital, analog, mixed-signal and radio-frequency (RF) functions. An SOC may use powerful processors that execute operating system (OS) software. In addition, the SOC may utilize hardware accelerators for digital signal processing (DSP) kernels, high-performance DSP cores, graphics processing units (GPUs), other single instruction multiple data (SIMD) cores and other proprietary processing cores. Further, the SOC may be connected to both external memory chips, such as Flash or RAM, and various external peripherals. Energy-constrained cellular phones, portable communication devices and entertainment audio/video (A/V) devices are some examples of systems using an SOC.
While executing applications, the various processor cores on the SOC may share system memory, buses and peripherals. In order to preserve system integrity, methods and mechanisms providing synchronization between the various processing cores and devices may be used. However, one or more of the cores or devices may lack multiprocessor synchronization support.
Additionally, the SOC may support 64-bit computing to meet modern demands for embedded systems. Although most desktops support 32-bit computing, most supercomputers, servers and other bigger systems utilize 64-bit computing, which is capable of addressing more memory. More memory may significantly improve performance of executing applications, such as those running in an embedded system. A synchronization scheme for a 64-bit SOC may utilize a 64-bit time base counter. Providing a 64-bit copy of this time base counter to each of the processing cores on the SOC consumes on-die real-estate with wire routes and storage elements for each of the processing cores. Further, as integration increases on a SOC, so does a number of different active clocks and a number of phase lock loops (PLLs) to support the clocks. These active clocks may operate at different frequencies from one another and from the source 64-bit time base counter.
In view of the above, efficient methods and mechanisms for synchronizing multiple processing cores on a system-on-a-chip (SOC) are desired.